1. Field of the Invention
The present invention relates generally to metal oxide semiconductor (MOS) transistors. It particularly relates to digital circuits involving MOS transistors that use ratioed logic.
2. Background Art
Metal Oxide Semiconductor (MOS) transistors have become very useful in digital circuit applications, particularly very-large-scale integrated circuits (VLSI) such as microprocessors and memories due to their small size, high switching speed, and ease of fabrication. Transistors are vital to microprocessor development since a typical microprocessor includes millions of transistors in its digital circuitry. The Intel Pentium(copyright) II processor and the IBM(copyright) POWER PC are illustrative examples of these high-end microprocessors.
Complementary MOS (CMOS) uses both P-channel and N-channel MOS transistors in its circuits. An important CMOS circuit, due to its advantageous characteristics, is the CMOS inverter. The circuit representation for a CMOS inverter 200 is shown in FIG. 1. CMOS inverter 200 typically includes PMOS transistor 210 coupled source-to-drain between a first node 205 and an output node 240. CMOS inverter 200 also typically includes NMOS transistor 220 coupled drain-to-source between the output node 240 and a second node 208 and further includes an input node 230 coupled to the gate of each transistor. Typically, the first node 205 is a positive voltage supply (e.g., Vdd) and the second node 208 is ground. PMOS transistor 210 and NMOS transistor 220 effectively form at least two switchable conductive paths that either create a connection to the next coupled node when the transistor is active (turned on) or create an open circuit when the transistor is inactive (turned off). The circuit is aptly named an inverter for when an input signal I applied to input node 230 is in a high state (e.g., logic level xe2x80x9c1xe2x80x9d), PMOS transistor 210 is off and the output node 240 is pulled low (e.g., logic level xe2x80x9c0xe2x80x9d) since the output node 240 is coupled to ground through the active NMOS transistor. Conversely, the output node 240 is pulled high (e.g., logic level xe2x80x9c1xe2x80x9d) when an input signal I applied to input node 230 is in a low state (e.g., logic level xe2x80x9c0xe2x80x9d) since the output node 240 is coupled to the positive voltage through the active PMOS transistor. In this particular circuit arrangement, PMOS transistors are commonly referred to xe2x80x9cPull-upxe2x80x9d transistors and NMOS transistors are referred to xe2x80x9cPull-downxe2x80x9d transistors due to their particular connection paths to a positive voltage and ground, respectively.
For higher switching speeds and to increase circuit performance, dynamic logic structures such as domino logic or ratioed logic have been used. Ratioed logic describes a CMOS circuit typically comprising a plurality of PMOS and NMOS transistors wherein the PMOS transistor and the NMOS transistor are contending with each other on a particular node when any one or more of the NMOS transistors are on. Consequently, ratioed CMOS circuitry depends strongly on the relative geometric sizes (particularly channel widths) of the PMOS and NMOS transistors. Conversely, ratioless logic designs have circuit characteristics (e.g., voltage transfer) that do not depend strongly on the relative geometric sizes of the PMOS and NMOS transistors.
The CMOS inverter structure is also commonly used in ratioed logic. The circuit speed of the CMOS inverter is the speed with which the PMOS and NMOS transistors of a CMOS inverter can respectively pull the output node toward one voltage or another (e.g., delay of the inverter) and is directly related to the size of the two transistors (e.g., driving and driven transistor). This competing relationship is often related to the ratio of the size of the channel widths of the PMOS transistor to that of the NMOS transistor. In a multiple stage CMOS logic structure, the PMOS and NMOS transistors are sized (via respective channel widths) such that any one NMOS transistor can drive the output to ground for one or two active PMOS transistors. Typically, in ratioed CMOS circuitry, this ratio of PMOS-to-NMOS transistor channel widths (Wp/Wn) is also carefully chosen to determine the respective on-resistances and threshold voltages (turn-on voltage) which will advantageously affect the transition delay and switching speeds of these devices. The advantages of ratioed logic include increased switching speed, compact physical layout characteristic, reduction in propagation delay, and other advantages.
Despite these advantages, there still remain problems with ratioed logic design which include power consumption, noise margin, and easily scaleable ratio stage gain. Therefore, there is a need to employ digital circuit designs using ratioed logic that help solve these problems.